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Intel 18A-P Enters Risk Production, Promises 9% Performance Improvement

Intel unveiled details of its 18A-P process during VLSI 2026 and announced its transition to the risk production phase, offering a 9% performance boost at the same power levels and introducing new transistor designs.

7 min read Reviewed & edited by the SINGULISM Editorial Team

Intel 18A-P Enters Risk Production, Promises 9% Performance Improvement
Photo by Slejven Djurakovic on Unsplash

Intel has announced that its optimized advanced semiconductor process, known as “18A-P,” has entered the risk production phase. During the international semiconductor conference VLSI 2026, the company revealed new transistor designs and performance data. The 18A-P process maintains backward compatibility with the existing 18A design while achieving a 9% performance improvement at the same power levels or an 18% reduction in power consumption at the same performance level.

Understanding Risk Production

Risk production is the semiconductor manufacturing phase that precedes full-scale mass production. Limited quantities of wafers are produced using standard production lines to gather data on defect rates, yield levels, and performance variability. Typically, advanced logic processes require 12–24 months to transition from risk production to mass production. However, since 18A-P is a derivative of the 18A process, it is expected to transition to full production in a shorter timeframe.

During the risk production phase, Intel collects diverse data on defect density (D0), process control monitor (PCM) stability, temperature characteristics, and reliability tests. This data is utilized to fine-tune the process before commencing full-scale production.

Details of Performance Improvement

Intel calculated the performance figures based on tests conducted at a standard voltage condition of 0.75V using standard Arm core sub-blocks. At the same power level, the operating frequency increased by 9%, while at the same frequency, power consumption was reduced by 18%. Intel also noted that these improvements in frequency and power efficiency are maintained even when the voltage fluctuates around 0.75V.

Graphs presented at VLSI 2026 confirmed the advantages of the 18A-P process across a wide voltage range. According to Intel’s study, consistent improvements were observed between 0.65V and 0.85V. This indicates that 18A-P boasts superior characteristics not only in power isolation performance but across its entire operating voltage range.

New Transistor Designs

Three new transistor designs have been added to the 18A-P library:

W1 Design: This high-performance design is now available in the 180nm cell height library. Previously, it was only offered in the high-density 160nm library. The narrow-width design is optimized for low power consumption and helps reduce leakage current.

W1.5 Design: This design is available in the high-density 160nm cell height library and, like W1, features a narrow-width design. It addresses gaps in the power-saving capabilities of Intel’s transistor library.

W3P Design: This new dual-contact transistor is available in both the 180nm and 160nm libraries. It features a functionality that Intel refers to as “Power Boost.” While specific structural details remain undisclosed, it is expected to contribute to lowering contact resistance and enhancing driving capabilities.

With these new designs, Intel has expanded its library to accommodate a wide range of design requirements, from low power consumption to high performance. In particular, the dual-contact structure of W3P is anticipated to significantly improve current driving capabilities compared to traditional single-contact designs.

Backward Compatibility

The 18A-P process maintains the same cell heights (180nm for high performance, 160nm for high density) as the 18A process, allowing existing designs created for 18A to be seamlessly ported to 18A-P without modifications. While the new transistor options offer additional performance gains, their use is not mandatory.

This backward compatibility ensures that all products designed for the 18A process can be manufactured using the 18A-P process without requiring design changes. This minimizes transition barriers for Intel’s customers, making it easier to reuse design assets and facilitating a smooth shift from risk production to full-scale manufacturing.

Connection to Product Roadmap

Intel plans to use the 18A process for its next-generation mobile SoC “Panther Lake” and server-oriented Xeon 6+ products. The 18A-P process will directly contribute to boosting performance and improving power efficiency for these products. For servers, the 18% reduction in power consumption could significantly lower the total cost of ownership (TCO) for data centers.

In the mobile segment, a 9% performance improvement could enhance application processor responsiveness and extend battery life. The data collected during the risk production phase will be used to improve yield rates and adjust the process before full-scale production begins.

Impact on the Industry

In the semiconductor industry, TSMC is set to begin mass production of its N2 (2nm-class) process in the second half of 2025, while Samsung is advancing its SF2 (2nm-class) process. Intel’s 18A and 18A-P processes are designed to compete with these cutting-edge technologies, and the performance improvements offered by 18A-P could strengthen Intel Foundry’s competitiveness.

The backward compatibility of 18A-P also ensures an easy transition for existing 18A customers, reducing yield risks and promoting the reuse of design assets. Intel aims to expand its foundry business, and the performance data from 18A-P will serve as a key selling point in attracting new customers.

Technical Background

18A-P is positioned as part of Intel’s Trailblazing Architecture initiative. The company introduced RibbonFET (GAAFET) and PowerVia (backside power delivery) technologies with the 18A process, and 18A-P is expected to inherit these foundational technologies. The new transistor designs further optimize performance on this established foundation.

The cell heights of 18A-P (180nm/160nm) are significantly reduced compared to those of Intel 4 and Intel 3, contributing to higher integration density. The performance optimization achieved with 18A-P is notable for being accomplished through improvements in transistor design while maintaining the same cell heights.

Future Outlook

With the transition to the risk production phase, Intel is expected to accelerate its move toward full-scale production in the coming months. The exact timeline for 18A-P’s mass production has not been disclosed, but it is likely to align with the market launch of Panther Lake and Xeon 6+ products.

Intel must ensure yield stability and performance consistency for 18A-P while accumulating comparative data that highlights its advantages over competitors like TSMC’s N2 and Samsung’s SF2 processes. The smooth transition from risk production to full production will be critical to maintaining confidence in Intel’s overall product roadmap.

Editorial Opinion

In the short term, the transition to the risk production phase for 18A-P demonstrates Intel’s confidence in its product roadmap. The key focus will be on whether mass production of Panther Lake and Xeon 6+ will proceed as planned between late 2026 and 2027. In the server market, the potential for an 18% reduction in power consumption represents a significant selling point, directly impacting data center operational costs. However, the extent to which yield data collected during the risk production phase is favorable could influence the timeline for subsequent steps.

From a long-term perspective, as semiconductor process scaling approaches physical limits, Intel is differentiating itself by introducing new transistor designs in 18A-P, such as W3P’s dual-contact structure. This approach, which enhances performance within the framework of traditional transistor architectures, is noteworthy. The success of Intel’s foundry business expansion will hinge on the yield and performance stability of 18A-P. Moreover, the ease of backward compatibility could play a crucial role in attracting foundry customers to adopt 18A-P technology.

The editorial team also raises questions about whether Intel can successfully establish a reliable mass production system and clearly demonstrate performance advantages over competing processes like TSMC N2 and Samsung SF2. While backward compatibility is an advantage for existing customers, Intel must also ensure that the added value provided by new transistor options is compelling enough to drive design changes and attract new customers. How well Intel leverages the achievements of 18A-P to grow its foundry business will significantly shape the future of the semiconductor industry.

References

Frequently Asked Questions

What is the risk production phase?
Risk production is the low-volume manufacturing stage carried out just before full-scale production. It involves producing limited quantities of wafers on standard production lines to collect data on defect rates, yield, and performance variability. While advanced logic processes typically take 12–24 months to transition from this phase to mass production, derivative processes often require less time.
How does 18A-P differ from 18A?
18A-P is an optimized version of 18A, maintaining the same cell heights and backward compatibility. It achieves a 9% performance improvement at the same power levels or reduces power consumption by 18% at the same performance levels. Additionally, it introduces three new transistor designs: W1, W1.5, and W3P, with W3P featuring a dual-contact structure and Power Boost functionality.
When will the mass production of 18A-P begin?
While Intel has announced that 18A-P has entered risk production, the exact timeline for full-scale production has not been disclosed. However, being a derivative process of 18A, 18A-P is expected to transition to full production more quickly than a brand-new node. The timeline is likely to coincide with the launch of Panther Lake and Xeon 6+ products.
Source: Tom's Hardware

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