Peking University Develops 3D Design Tools for Huawei's LogicFolding Architecture

The Institute of Integrated Circuits at Peking University in China has unveiled a prototype of an electronic design automation (EDA) tool specifically tailored for Huawei’s new semiconductor architecture, “LogicFolding,” according to local media reports. This tool adopts a “true 3D approach,” expanding conventional 2D chip designs into three dimensions, reducing internal wiring length by up to 30%, and simultaneously improving performance and heat dissipation efficiency. The announcement came just two days after Huawei showcased its LogicFolding architecture and its theoretical foundation, the “Tau Scaling Law,” at the IEEE International Symposium on Circuits and Systems (ISCAS 2026) in Shanghai. Huawei has set ambitious targets to produce chips with transistor densities equivalent to the 1.4nm process by 2031, without relying on extreme ultraviolet (EUV) lithography equipment restricted under U.S. export controls.

What is LogicFolding?

LogicFolding is an innovative architecture that transforms traditional planar circuit layouts into vertically folded, three-dimensional stack structures. This approach significantly shortens the physical pathways through which electrical signals travel within a chip. By reducing wiring resistance and capacitance, signal propagation delays are minimized, leading to improved operational frequencies and reduced power consumption. According to Huawei, the upcoming Kirin smartphone processor set to launch later this year will be the first commercial chip to incorporate this architecture. For Huawei, which faces restrictions on acquiring advanced EUV lithography equipment due to U.S. sanctions, breakthroughs in design are seen as a critical strategy to overcome manufacturing node limitations.

How Does It Differ From Conventional 3D IC

Design? Major EDA vendors like Synopsys and Cadence already offer platforms for designing 3D integrated circuits. However, these tools primarily support “package-level” 3D integration, which involves stacking and integrating multiple chiplets or dies within the same package. LogicFolding, on the other hand, focuses on vertical folding of circuits at the transistor level within a single chip. Known as “intra-die optimization,” this approach treats the entire multilayer structure as a unified design space from the outset, allowing simultaneous place-and-route across all vertical layers. According to researchers at Peking University, initial tests of the prototype tool using open-source circuit designs showed a 30% reduction in internal wiring length compared to conventional EDA workflows. Additionally, improvements were confirmed in both performance and heat dissipation management. However, further validation is needed to determine whether these results can be replicated on a mass production scale.

The Global EDA Market and China’s Dependency

The global EDA market is dominated by three major players: Synopsys (31% market share), Cadence (30%), and Siemens EDA (13%), which together control about two-thirds of the market. In China alone, these three companies account for over 80% of the domestic market, according to EE Times China. Last year, the U.S. partially restricted the export of certain EDA tools to China as part of its broader trade restrictions. Although these restrictions were later lifted following agreements related to rare earth trade, the incident highlighted Chinese chipmakers’ heavy reliance on Western tools. The recent initiative by Peking University represents a noteworthy example of China’s efforts to foster its domestic EDA industry.

Challenges and Future Prospects The tool

developed by Peking University is still in the prototype stage and has not yet achieved the maturity required for commercial EDA products. Significant hurdles remain, particularly in applying the tool to large-scale system-on-chip (SoC) designs and integrating it with existing design workflows. Huawei is also working to ensure manufacturing compatibility and reliability for mass production of LogicFolding-based chips. Despite these challenges, the collaboration between Peking University and Huawei symbolizes an important step for China’s semiconductor industry as it seeks greater technological independence in the face of U.S. export restrictions. The theoretical framework provided by the Tau Scaling Law, combined with the practical application of the EDA tool, could pave the way for a new scaling paradigm akin to a “Chinese version of Moore’s Law.” The upcoming focus will be on assessing the extent to which this tool can enhance actual chip designs and whether it can compete with the established ecosystem dominated by Synopsys and Cadence. Under China’s national strategy to strengthen its semiconductor supply chain, Peking University and Huawei are expected to continue their close collaboration.