AMD Submits AVX10_V2_AUX Support Patches to GCC

AMD’s compiler engineer has submitted AVX10_V2_AUX ISA support patches to the GNU Compiler Collection (GCC). This instruction set extension is aimed at accelerating AI workloads by providing conversion capabilities for compressed data formats such as FP4 and FP6. This submission follows Intel’s AI Compute Extensions (ACE) patches earlier this month, underscoring the collaborative relationship between the two companies within the x86 Ecosystem Advisory Group.

According to a report by Phoronix’s Michael Larabel, the patch series posted by AMD engineer Dipesh Sharma comprises seven commits. These patches add support for CPUID detection, built-in functions, and intrinsics. AVX10_V2_AUX supports data format conversions such as FP32 to FP8, FP8 to FP4, and FP8 to FP6, as well as reverse conversions.

Context of ACE and the x86 Advisory Group

Earlier this month, Intel’s compiler engineers submitted initial ACE patches to GCC. ACE is a specification developed under the x86 Ecosystem Advisory Group that introduces new features for AI/ML workloads to both AVX and scalar code. AVX10_V2_AUX is positioned as part of this ACE v1 specification, adding instructions for converting standard data types into compressed data formats, supporting OCP micro-scaling formats, and introducing new rounding modes.

The x86 Ecosystem Advisory Group is an industry organization jointly established by Intel and AMD. While the two companies remain competitors, the group was created to strengthen the common foundation of the x86 architecture. Instruction set extensions for accommodating the growth in AI workloads have become one of the group’s key focus areas.

Technical Details of AVX10_V2_AUX

The primary feature added by AVX10_V2_AUX pertains to data format conversion. Notably, it supports compressed data formats such as FP8 (8-bit floating point), FP4 (4-bit floating point), and FP6 (6-bit floating point). These low-precision formats contribute to reducing memory usage and improving computational speed in AI model inference and training.

Support for the OCP (Open Compute Project) micro-scaling format is also included. This standardized numerical representation format is crucial for ensuring compatibility across different hardware platforms in data centers. Additionally, the new rounding modes offer greater flexibility in controlling numerical precision during AI computations.

Dipesh Sharma’s patch submission includes the following description:

“This series of seven patches adds support for CPUID detection, built-ins, and intrinsics for the AVX10_V2_AUX instructions. AVX10_V2_AUX is a new ISA for x86 that supports conversions between FP32-FP8, FP8-FP4, FP8-FP6, and their reverse directions.”

Implementation Status and Schedule for GCC

Currently, these patches are under review on the GCC compiler mailing list. Considering the GCC development cycle, full support for ACE v1 is likely to be merged into the stable GCC 17.1 release, scheduled for next year.

GCC is a standard compiler used in Linux and many open-source projects. The addition of AVX10_V2_AUX support will allow developers to utilize new AI-oriented instructions directly in their C/C++ code. This eliminates the need for manual assembly writing or inline assembly, enabling more efficient code generation.

Significance of Collaboration in the x86

Ecosystem

The collaboration between Intel and AMD on the same instruction set extension carries significant implications for the x86 platform as a whole. By establishing a common foundation, the software ecosystem can target a single instruction set, allowing developers to write AI-optimized code without needing to differentiate between Intel and AMD CPUs.

This initiative can also be seen as a strategy for the x86 architecture to maintain competitiveness against alternative architectures like ARM and RISC-V. Particularly in AI inference workloads for edge devices and data centers, a unified instruction set extension directly strengthens the ecosystem.

Outlook for GCC 17.1

Given that the patches are still under review, the timeline for merging them into GCC 17.1 will be tight. However, with engineers from both Intel and AMD collaboratively advancing the development, it is likely to be treated as a high-priority feature.

If GCC 17.1 is released next year, a compiler capable of generating binaries with AVX10_V2_AUX support will become widely available. This will enable AI/ML libraries and frameworks to further optimize using the new instruction set.

Additionally, AMD has been increasing its presence in the CPU market. Recently, AMD’s Medusa Point achieved the fastest single-core x86 record on Geekbench. By advancing both compiler infrastructure and CPU performance simultaneously, AMD is poised to strengthen its platform’s competitiveness even further.

Editorial Opinion

In the short term, this patch submission represents a preparatory step toward GCC 17.1. While it may take several months of review and revisions before being merged, the fact that both Intel and AMD have submitted ACE-related patches in the same timeframe indicates that the x86 Ecosystem Advisory Group is functioning effectively. Over the next 3–6 months, more detailed specifications and benchmark results are likely to emerge.

In the long term, common instruction set extensions like AVX10_V2_AUX will become critical for x86 architecture’s AI capabilities. Support for ultra-low precision formats like FP4 and FP6 is expected to deliver significant benefits in inference workloads, where memory bandwidth is often a bottleneck. As competition with ARM’s Scalable Vector Extensions (SVE) and RISC-V’s vector extensions intensifies, x86’s ability to maintain its market share in AI will depend on the speed of foundational technology development.

References

• “AMD Posts AVX10_V2_AUX ISA Support Patches For GCC Compiler”, by Michael Larabel — Phoronix, 2026-07-20T10:27:06.000Z (ARR)
• Source URL: https://www.phoronix.com/news/GCC-AVX10-V2-AUX-Patches