TSMC Embarking on Largest Semiconductor Expansion in History with Multi-Site N2 Volume Production
TSMC begins industry's largest manufacturing capacity expansion. Simultaneously ramping N2 process at five fabs, boosting CoWoS and SoIC packaging capabilities to meet AI accelerator demand.
Taiwan Semiconductor Manufacturing Company (TSMC) is executing the largest manufacturing capacity expansion plan in semiconductor industry history. According to details revealed at the company’s 2026 Technology Symposium, TSMC is combining a multi-site simultaneous ramp of N2 process technology, a massive increase in advanced packaging technologies like CoWoS (Chip-on-Wafer-on-Substrate) and SoIC (System-on-Integrated-Chips), and AI-driven manufacturing optimization to build a system capable of meeting surging demand for AI accelerators.
$240 Billion Investment Over the Past Decade
According to a report from Tom’s Hardware, TSMC has invested approximately $240 billion over the past ten years to expand capacity. It now operates dozens of 300mm fabs across nine sites, with wafer processing capacity for advanced processes using EUV lithography that exceeds Intel’s. TSMC has established itself not merely as the “world’s largest foundry” but as the “world’s largest manufacturer of advanced logic chips.”
TSMC’s competitive advantage relies not only on process technology but also on production capacity. To counter Intel Foundry and Samsung Foundry, the company is pursuing fab construction and equipment installation at an unprecedented pace.
Construction Pace Doubled to Nine Phases per Year
From 2025 to 2026, TSMC has effectively doubled its construction pace. The company has increased fab construction from an average of four phases per year to nine phases currently. New fabs are being built or ramped simultaneously in Taiwan, Arizona (USA), Kumamoto (Japan), and Dresden (Germany).
According to TSMC’s presentation materials, the main sites currently in operation or under ramp include:
- Fab 20 Phases 1 & 2 (N2): Hsinchu, Taiwan — Under ramp
- Fab 21 Phase 2 (N3): Arizona, USA — Equipment installation in progress
- Fab 21 Phases 3 & 4 (N2): Arizona, USA — Under construction
- Fab 22 Phase 1 (N2): Kaohsiung, Taiwan — Under ramp
- Fab 22 Phases 2 & 3 (N2): Kaohsiung, Taiwan — Equipment installation and ramp scheduled for late 2026
- Fab 23 (JASM Phase 2, up to N3): Kumamoto, Japan — Under construction as of January 2025, though work was temporarily stalled
- Fab 24 (ESMC Phase 1, N12/N16/N22/N28): Dresden, Germany — Under construction as of August 2024
- Fab 25 Phase 1 (A14/A13/A12): Taichung, Taiwan — Under construction
Unprecedented N2 Process:
Simultaneous Volume Production at Five Sites
The N2 process lies at the heart of TSMC’s expansion plan. The company has already started volume production of N2 at two sites: Fab 20 Phases 1 & 2 in Hsinchu and Fab 22 Phase 1 in Kaohsiung. It is extremely unusual for a foundry to simultaneously ramp a leading-edge node at three facilities.
Additionally, within 2026, Fab 22 Phase 2 and Phase 3 in Kaohsiung will also begin volume production, eventually expanding to Phase 4. As a result, the N2 process will be in volume production at up to five fabs within its first year — a scale unprecedented in the semiconductor industry.
TSMC plans to increase N2-based wafer production capacity to several hundred thousand wafers per month by 2029. This figure will be larger than any node the company has ever achieved.
CoWoS and SoIC: Boosting Packaging Capacity
Driven by rising demand for AI accelerators, TSMC is also aggressively expanding capacity for advanced packaging technologies such as CoWoS and SoIC. CoWoS is the primary packaging technology used for NVIDIA and AMD AI GPUs, while SoIC enables high-density interconnects between chiplets.
In addition to improving productivity at existing packaging fabs, TSMC is building new dedicated packaging fabs. The company aims to meet demand not only for AI accelerators but also for chips used in HPC (high-performance computing) and networking.
AI-Driven Manufacturing Optimization
Alongside fab construction, TSMC is optimizing manufacturing processes using AI. Specifically, the company is deploying AI models for yield improvement, schedule optimization, and predictive equipment maintenance. The goal is to boost productivity at existing facilities.
By maintaining its fab construction pace while combining AI-driven operational efficiency, TSMC aims to flexibly respond to surging demand.
Global Expansion and Geopolitical Risks
TSMC’s expansion extends beyond Taiwan to the United States, Japan, and Germany. Notably, in Arizona, after Phase 1 (N4 process), subsequent phases will introduce N3 and N2 processes. In Kumamoto, Japan, JASM Phase 2 will support the N3 process; although construction was temporarily stalled, progress is being watched closely.
The ESMC (European Semiconductor Manufacturing Company) in Dresden, Germany, will handle mature nodes (N12/N16/N22/N28) for the automotive industry. This also addresses geopolitical demands for increased semiconductor self-sufficiency in Europe.
However, construction delays and geopolitical uncertainties remain. Tensions in the Taiwan Strait, in particular, could affect TSMC’s global strategy.
Editorial Opinion
In the short term, the simultaneous ramp of TSMC’s N2 process at five sites could significantly improve the supply of AI accelerators by mid-2027. This is likely to help alleviate GPU shortages currently faced by NVIDIA, AMD, Google, and Amazon. On the other hand, the increase in amortization costs due to massive investments poses a risk that could pressure TSMC’s profitability. The next quarterly earnings report will be closely watched for yield progress and cash flow status.
From a long-term perspective, TSMC’s expansion strategy has the potential to redraw the semiconductor industry map. Development of next-generation nodes beyond N2 — A14, A13, and A12 — is proceeding in parallel. If TSMC achieves N2 capacity of several hundred thousand wafers per month by 2029, competitors Intel Foundry and Samsung Foundry will face further scale disadvantages. Additionally, the expansion of CoWoS and SoIC packaging capacity could accelerate the adoption of chiplet architectures, triggering a paradigm shift in overall system design.
Our editorial view is that the success of TSMC’s expansion will heavily depend on the procurement of construction materials and equipment, securing skilled engineers, and geopolitical stability. In particular, the intensification of US-China tensions raising the risk of a Taiwan contingency remains the biggest uncertainty for TSMC’s management. We recommend that readers reassess the supply chain strategies of companies with exposure to TSMC.
References
Frequently Asked Questions
- When will TSMC's N2 process begin volume production?
- Volume production has already started at Fab 20 Phases 1 and 2 in Hsinchu and Fab 22 Phase 1 in Kaohsiung. By the end of 2026, Fab 22 Phases 2 and 3 in Kaohsiung will be added, bringing the total to five sites in volume production.
- What is the difference between CoWoS and SoIC?
- CoWoS is a technology that packages multiple chips on a silicon interposer, primarily used for AI GPUs. SoIC is a technology that directly bonds chips together with higher density, suitable for 3D stacking. Both are core to TSMC's advanced packaging.
- How will TSMC's overseas fab expansion affect Japan and the United States?
- The Arizona fab in the US plans to introduce N3 and N2 processes, significantly increasing local semiconductor production capacity. The Kumamoto fab in Japan will support up to N3, contributing to stable supply of chips for automotive and industrial sectors. Both will advance each country's semiconductor self-sufficiency.
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